Floorplanning with Pin Assignment

We present a hierarchical technique for floorplanning and pin assignment of the general cell layouts. Given a set of cells with their shape lists, a layout aspect ratio, relative positions of the extemal 110 pads and upper bound delay constraints for a set of critical nets, we determine shapes and positions of the cells, locations of the floating pins on cells and a global routing solution such that a linear combination of the layout area, the total interconnection length and constraint violations for critical nets is minimized. Floorplanning, pin assignment and global routing influence one another during the hierarchical steps of the algorithm. The pin assignment algorithm is flexible and allows various user specified constraints such as pre-specified pin locations, feedthrough pins, length-critical nets and planar net topologies. Placement, timing and floorplanning results for Xerox general cell benchmark are reported.